1. Technical Field of the Present Invention
The present invention generally relates to integrated circuits and, more specifically, to the design and modeling of the packaging used for the integrated circuit.
2. Description of Related Art
The insatiable appetite of the consumer for electronic devices that are increasingly smaller, faster, and contain more functionality than previous models has fueled the evolution of the electronic industry. Each one of these electronic devices contains one or more integrated circuit chips that range in complexity from a system on a chip to one or more dedicated processors.
This fast paced demand has challenged the semiconductor industry to decrease the amount of time that it takes to proceed from the design to production stage. Various simulation tools are used in this process to simulate different aspects of the integrated circuit and to create models that are representative of the behavior of the final product. These models have become an integral and indispensable part of the semiconductor design and verification process.
One such model is the integrated circuit electrical package model that represents the various electrical networks residing in the electronic package itself. Unfortunately, current models are inefficient for simulating power supply noise for integrated circuits and the simulation time is considerable.
It would, therefore, be a distinct advantage to have an electrical package model optimized for size so that shorter simulation times can be accomplished.